Tungsram - Integrated circuits '77 [antikvár]

TTL LOADING RULESAll Transistor Transistor Logic integrated circuits are derived from the simple gate schematic shown in Figure 1.The output is LOW (logic "0") only if both inputs A and B are HIGH (logic "1"). This is defined as a positive logic NAND gate.Input CharacteristicsA low voltage at inputs A or B will cause current to flow out of the forward biased base-emitter diode of the multi-emitter transistor (Ti). When the voltage level at A or 8 or both is less than 2 VbE(SAT) levels, the current supplied by Ri will flow out of the LOW input terminal (see Figure 2) keeping transistors Tq and T4 turned off. If both inputs A and B are raised to a HIGH voltage level, the base-emitter diodes of the input transistor (Ti) will be reverse biased. The current supplied by R-j will then flow through the base-collector diode of T-| (see Figure 3) turning on transistor T2 and t4. The HIGH level Input voltage source must be capable of supplying leakage current to the reverse biased Input transistor. Because of the NPN action of the input device, this leakage current is referred to as Inverse beta current. The value of the Input LOW current and input HIGH leakage current is dependent on the value of Rl. The value of this resistor Is chosen to optimize the specific speed/power performance characteristics of each device.figure 3Output CharacteristicsThe fan out or drive capability of a TTL device reflects Its ability to sink current in the output LOW (logic "0") state (see Figure 4) and to source or drive current in the output HIGH (logic "1") state (see Figure 5).In the output LOW state the "phase splitter" transistor 12 is "on". It supplies base drive to the output pull down transistor (T4). The amount of base drive required for the pull down transistor Is dependent on the worst case beta of the device and the fan out (Iql) current requirements of the circuit. The output high drive current (Iqh) of tbe device is supplied from the pull up transistor (T3I. When the phase splitter transistor (T2) is turned "off", the pull up transistor is turned "on". This presents a low impedance drive source at the output. Although the static Iqh requirements of most circuits is less than 0.5 mA, about 35 mA is made available at the instant of LOW to high output transition to charge up the distributed line, board and package capacitances encountered in most system designs. Different types of pull up circuits are used to achieve faster system speeds by minimizing high output impedance and the resulting RC time constant.Normalized Fan In/Fan Out RulesIn order to simplify designing with Fairchild TTL devices, the input and output loading parameters of all families are normalized to the following values:1 Unit TTL Load (U.L.) = 40/iA in the HIGH state (logic "1") = 1.6 mA in the LOW state (logic "0")Input loading and output drive factors of all products described in this catalog are related to these definitions.Examples Input Load1.A 9N00/7400 gate, which has a maximum l|i_ of 1.6 mA and 11H of 40 /jA is specified as having an input load factor of 1 U.L. (Also called a fan in of 1 load.)2.The 93H72, which has a value df I|l = 3.2 mA and I|H of 80/jA on the CP terminal, is specified as having an inputload factor of ^ g or 2 U.L.Examples Output Drive1. The output of the 9NOO/7400 will sink 16 mA in the LOW (logic "0"| state and source 800/uA in the HIGH (logic "1") state. The normalized output LOW drive factor istherefore10 U.L. and the output HIGH drivefac,oris^=20U.L.Relative load and drive factors for the basic TTL gate families specified in this catalog are given in Table 1.